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| SL74HC4015 Dual 4-Bit Shift Register High-Performance Silicon-Gate CMOS The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two identical independent 4-stage serialinput/parallel-output registers. Each register has independent Clock and Reset inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC4015N Plastic SL74HC4015D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Clock Data L PIN 16 = VCC PIN 8 = GND X * Outputs Reset L L L H Q0 L H Q0 L * Qn Qn-1 Qn-1 Qn* L H X X = No Change X = don't care SLS System Logic Semiconductor SL74HC4015 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC4015 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 8.0 85 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 80 125 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 160 A A V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT= 0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN= VIH or VIL IOUT 4.0 mA IOUT 5.2 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT 20 A VIN= VIH or VIL IOUT 4.0 mA IOUT 5.2 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VIN=VCC or GND IOUT=0A SLS System Logic Semiconductor SL74HC4015 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figure 2) Maximum Propagation Delay, Clock to Q (Figures 2 and 5) Maximum Propagation Delay, Reset to Q (Figures 1 and 5) Maximum Output Transition Time, Any Output (Figures 3 and 5) Maximum Input Capacitance Power Dissipation Capacitance (Per Latch) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 6 30 35 175 35 30 205 41 35 75 15 13 10 85C 4.8 24 28 220 44 37 255 51 43 95 19 16 10 125C 4 20 24 265 53 45 310 62 53 110 22 19 10 Unit MHz tPLH, t PHL ns tPHL ns tTLH, t THL ns CIN pF Typical @25C,VCC=5.0 V 140 pF TIMING REQUIREMENTS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tsu Parameter Minimum Setup Time, D to Clock (Figure 4) Minimum Hold Time, Clock to D (Figure 4) Minimum Recovery Time, Reset to Clock (Figure 1) Minimum Pulse Width, Reset (Figure 1) Minimum Pulse Width, Clock (Figure 4) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 50 10 9.0 5 5 5 5 5 5 80 16 14 80 16 14 1000 500 400 85C 65 13 11 5 5 5 5 5 5 100 20 17 100 20 17 1000 500 400 125C 75 15 13 5 5 5 5 5 5 120 24 20 120 24 20 1000 500 400 Unit ns th ns trec ns tw ns tw ns tr, t f ns SLS System Logic Semiconductor SL74HC4015 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Test Circuit SLS System Logic Semiconductor SL74HC4015 EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor |
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